Non-volatile memories are important elements of integrated circuits due to their ability to maintain data absent a power supply. Several different typical resistance memory elements using different materials have been suggested for such use. Variable resistance memory elements can be programmed to a resistance value as a way of storing logic data. One suggested type of resistance memory employs phase change materials such as chalcogenide alloys, which are capable of stably transitioning between amorphous and crystalline phases. Each phase exhibits a particular resistance state and the resistance states distinguish the logic values of the memory element. Specifically, an amorphous state exhibits a relatively high resistance, and a crystalline state exhibits a relatively low resistance.
FIG. 1A shows a basic composition of a variable resistance memory cell 10, which may be implemented using a variable resistance material, and which is constructed over a substrate 11. A variable resistance material 16 is formed between a bottom electrode 14 and a top electrode 18. The bottom electrode is located within an insulating layer 12. The material used to form the electrodes 14, 18 can be selected from a variety of conductive materials, such as tungsten, nickel, tantalum, titanium, titanium nitride, aluminum, platinum, or silver, among others.
Much research has focused on variable resistance memory devices using chalcogenides. Chalcogenides are alloys of Group VI elements of the periodic table, such as tellunium (“Te”) or selenium (“Se”) or germanium (“Ge”). A specific chalcogenide currently used in rewriteable compact discs (“CD-RWs”) is Ge2Sb2Te5. In addition to having valuable optical properties that are utilized in CD-RW discs, Ge2Sb2Te5 also has desirable physical properties as a variable resistance material, i.e., phase change material or GST material. For example, various combinations of Ge, antimony (“Sb”) and Te may be used as variable resistance materials. Specifically, GST material can change structural phases between an amorphous phase and two crystalline phases. The resistance of the amorphous phase (“a-GST”) and the resistances of the cubic and hexagonal crystalline phases (“c-GST” and “h-GST,” respectively) can differ significantly. The resistance of amorphous GST is greater than the resistances of either cubic GST or hexagonal GST, whose resistances are similar to each other. Thus, in comparing the resistances of the various phases of GST, GST may be considered a two-state material (amorphous GST and crystalline GST), with each state having a different resistance that can be equated with a corresponding binary state. A variable resistance material such as GST whose resistance changes according to its material phase is referred to as a phase change material. The transition from one GST phase to another occurs in response to temperature changes of the GST material.
In a variable resistance memory cell, heating and cooling of the GST material can occur by causing differing amplitudes of current to flow through the GST material. The GST material is placed in a crystalline state by passing a crystallizing current through the GST material, thus warming the GST material to a temperature wherein a crystalline structure may grow. A stronger melting current is used to melt the GST material for subsequent cooling to an amorphous state. As the typical phase change memory cell uses the crystalline state to represent one logic value, e.g., a binary “1,” and the amorphous state to represent another logic value, e.g., a binary “0,” the crystallizing current is typically referred to as a write current IW and the melting current is referred to as an erase or reset current IRST. One skilled in the art will understand, however, that the assignment of GST states to binary values may be switched if desired.
The state of the GST material is determined by applying a small read voltage Vr across the two electrodes and by measuring the resultant read current Ir. A lower read current Ir corresponds to a higher resistance Ir where the GST material is in an amorphous state and a relatively high read current Ir corresponds to a lower resistance where the GST material is in a crystalline state.
The phase-changing current is applied to the GST material via a pair of electrodes. In FIG. 1B, for example, the phase-changing currents are applied via the bottom electrode 14 and the top electrode 18. Because of the configurations of the bounding surface areas of the two electrodes 14, 18, current densities 50 within the GST material are not equally distributed. In particular, current densities 50 near the bottom electrode 14 are greater than the densities near the top electrode 18. Furthermore, areas of the GST material that are directly in between the two electrodes 14, 18 have higher current densities 50 than areas that are not directly in between the two electrodes 14, 18 such as areas near the lower corners of the GST material.
A sought after characteristic of non-volatile memory is low power consumption. Often, however, conventional variable resistance memory elements require large operating currents. It is therefore desirable to provide variable resistance memory elements with reduced current requirements. For variable resistance memory elements, it is necessary to have a current density that will heat the variable resistance material past its melting point and quench it in an amorphous state. One way to increase current density is to decrease the size of the bottom electrode. These methods maximize the current density at the bottom electrode interface to the variable resistance material. Although conventional solutions are typically successful, it is desirable to further reduce the overall current in the variable resistance memory element, thereby reducing power consumption in certain applications.